The present invention relates generally to integrated circuits. More particularly, the invention relates to a method and system for performing error correction in multi-level solid state non-volatile memories.
Solid state non-volatile memories, such as flash EEPROM memories, are used in a variety of electronics applications. Flash memories are used in a number of memory card formats, such as CompactFlash (CF), MultiMediaCard (MMC) and Secure Digital (SD). Electronic systems in which such cards are used include personal and notebook computers, hand-held computing devices, cameras, MP3 audio players, and the like. Flash EEPROM memories are also utilized as bulk mass storage in many host systems.
Conventional solid state memories store information as a series of binary digits or “bits,” which can take on one of two different values (0 or 1). Bits are grouped together to represent larger numbers.
As with most solid state non-volatile memory devices, flash EEPROMs are susceptible to defects and failures. Errors result from several factors including the gradual shifting of the threshold level of the memory states as a result of ambient conditions and stress from normal operations of the memory device including program, erase, and read operations. In order to prevent errors during operation, error correction code (ECC) techniques are utilized in flash memory devices. Typically, a controller generates redundant bits (parity bits) that are appended to the end of data sectors during program operations. For example, a 512 byte data sector may have 16 bytes of ECC data appended, resulting in a 528 byte page. During read operations, the redundant data included in the 16 bytes of ECC data is utilized to detect and correct errors in the data read out from the flash memory.
For a conventional memory, the maximum storage density is determined by the size of the individual storage elements and the number of storage elements that can be integrated onto a single integrated circuit chip. Typically, increases in memory density have been provided by shrinking the linewidth of the process geometry used to fabricate the memory cells.
Another technique used to increase solid state non-volatile memory density is storing more than one bit per memory cell, also referred to as a multi-level memory cell. Rather than sensing whether or not charge is stored in a given memory cell (i.e., a binary cell), multi-level memories utilize a sense amplifier that senses the amount of charge stored in a capacitive storage cell. By quantizing information into units greater than binary, e.g., 4-level (2 bits/cell), 8-level (3 bits/cell), 16-level (4 bits/cell) units, and the like, and storing these multi-level units, the memory density can be increased. As an example, a cell may be programmed to produce four distinct threshold levels, which results in four distinct read-back levels. With a four level signal available per cell, two data bits can be encoded into each solid state non-volatile memory cell. Multi-level memories enable the manufacturing of higher density memories without increasing the number of memory cells since each memory cell can store more than a single bit. Merely by way of example, for a memory cell capable of storing 2 bits/cell, there may be three programmed states and an erased state. FIG. 1 is a simplified probability distribution function (PDF) as a function of voltage for a solid state non-volatile memory cell having a 4-level quantization. In the memory cell illustrated in FIG. 1, four programmed states are utilized. As illustrated, in some solid state non-volatile memories, the PDF of programming characteristics has a wider distribution at lower voltage levels.
However, increasing the number of quantization levels in a cell results in a reduction in the voltage difference between adjacent levels. In multi-level encoding systems, this reduction is sometimes referred to as reduced signal distance (reduced Dmin). Reduced signal distance may impact non-volatile memory performance in both write (program) as well as read operations. During programming, it is more difficult to transfer multiple discrete units of charge to a capacitive cell than it is simply to fully charge or fully discharge the cell. Thus, uncertainty in the amount of charge transferred to a given cell may result in a level shift, resulting in a “program disturb” in which the wrong level is stored in the cell. During reading, “read disturbs” occur when the distribution of one signal level overlaps the distribution of an adjacent signal level. Because the signal distance is reduced, the increase in the number of discrete values stored in the cell reduces the noise margin of the cell as compared to a binary storage cell, making the storage element more prone to erroneous readout. Read disturbs are more common for low-level signals, which are characterized by larger noise distributions as shown in FIG. 1.
The reduction in voltage separation between adjacent levels in a multi-level solid state non-volatile memory may lead to an increase in the number of errors in comparison with conventional solid state non-volatile memory cells. Thus, it would be desirable to provide improved methods and techniques for operating solid state non-volatile memory with multi-level cells.